1. Field of the Invention
The present invention relates to techniques for improving the performance of computer systems. More specifically, the present invention relates to a method and an apparatus for enforcing memory barrier (membar) instruction semantics in a processor during execute-ahead mode, wherein instructions that cannot be executed because of unresolved data dependencies are deferred, and other non-deferred instructions are executed in program order.
2. Related Art
Advances in semiconductor fabrication technology have given rise to dramatic increases in microprocessor clock speeds. This increase in microprocessor clock speeds has not been matched by a corresponding increase in memory access speeds. Hence, the disparity between microprocessor clock speeds and memory access speeds continues to grow, and is beginning to create significant performance problems. Execution profiles for fast microprocessor systems show that a large fraction of execution time is spent not within the microprocessor core, but within memory structures outside of the microprocessor core. This means that the microprocessor systems spend a large fraction of time waiting for memory references to complete instead of performing computational operations.
Efficient caching schemes can help reduce the number of memory accesses that are performed. However, when a memory reference, such as a load operation generates a cache miss, the subsequent access to level-two cache or main memory can require dozens or hundreds of clock cycles to complete, during which time the processor is typically idle, performing no useful work.
A number of techniques are presently used (or have been proposed) to hide this cache-miss latency. Some processors support out-of-order execution, in which instructions are kept in an issue queue, and are issued “out-of-order” when operands become available. Unfortunately, existing out-of-order designs have a hardware complexity that grows quadratically with the size of the issue queue. Practically speaking, this constraint limits the number of entries in the issue queue to one or two hundred, which is not sufficient to hide memory latencies as processors continue to get faster. Moreover, constraints on the number of physical registers that are available for register renaming purposes during out-of-order execution also limits the effective size of the issue queue.
Some processor designers have proposed entering an execute-ahead mode during processor stall conditions. In this execute-ahead mode, data dependent instructions are deferred while non-data-dependent instructions are executed in program order. For example, see U.S. patent application Ser. No. 10/686,061, filed 14 Oct. 2003, entitled “Selectively Deferring the Execution of Instructions with Unresolved Data Dependencies as They Are Issued in Program Order,” by inventors Shailender Chaudhry, Marc Tremblay and Quinn A. Jacobson. By continuing to perform work during stall conditions, this technique can significantly increase the amount of work that can be completed by a processor.
Certain processors provide a type of instruction known as a memory barrier (membar) that gives programmers the ability to force a deterministic memory state on the system. For example, one common membar instruction forces a deterministic memory state by stalling the system until all buffered stores and loads are completed. Once the buffered loads and stores have completed, the processor can execute subsequent instructions with the assumption that all preceding memory references have completed. While useful and necessary, membar instructions can take an extremely long time to complete because the system may have to wait for large numbers of loads and stores to complete.
Hence, what is needed is a method and an apparatus for enforcing membar instruction semantics in an execute-ahead processor without the above-described performance problems.